A 585.9 μW complementary VCO with an LC head-and-tail filtering achieving 196.7 dBc/Hz FoM
This paper reports a PMOS-NMOS Complementary LC voltage-biased oscillator with dual-second harmonic filtering tanks. It features 2 LC networks integrated each at the head and tail of the oscillator to concurrently resonate at twice the oscillating frequency (f(LO)), forming two high-impedance paths...
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| Main Authors: | , , |
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| Format: | Article |
| Published: |
Taylor and Francis Ltd.
2024
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| Subjects: | |
| Online Access: | http://eprints.um.edu.my/46078/ |
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| Institution: | Universiti Malaya |
| Summary: | This paper reports a PMOS-NMOS Complementary LC voltage-biased oscillator with dual-second harmonic filtering tanks. It features 2 LC networks integrated each at the head and tail of the oscillator to concurrently resonate at twice the oscillating frequency (f(LO)), forming two high-impedance paths to prevent the PMOS and NMOS -g(m) differential pairs from loading the main LC resonator when the transistors are driven into the triode region. This improves the voltage and current efficiency of the oscillator. Furthermore, the gate-to-source voltages of the two -g(m) differential pairs are reshaped to reduce their phase noise contributions. Simulated in 65 nm CMOS, the proposed oscillator with 4.64-5.64 GHz (17.68%) tunability exhibits a power consumption ranging 585.9-655.4 mu W while offering a phase noise performance of -139-141.5 dBc/Hz at the 10 MHz offset. The corresponding FoM is 196.2-196.7 dBc/Hz. |
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