DC link capacitor voltage balancing in three level neutral point clamped inverter

• Main Authors: Mekhilef, Saad, Khudhur, H.I., Belkamel, H.
• Format: Conference or Workshop Item
• Language: English
• Published: 2012
• Subjects: TA Engineering (General). Civil engineering (General); TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.um.edu.my/4716/1/DC_link_capacitor_voltage_balancing_in_three_level_neutral_point_clamped_inverter.pdf; http://eprints.um.edu.my/4716/; http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6251754
• Institution: Universiti Malaya

Multilevel inverters are becoming increasingly popular for high and medium power applications. The diode clamped multilevel inverter (DCMLI) is an attractive high voltage multilevel inverter due to its robustness. The deviating voltage at the neutral point remains always a distracting feature in NPC inverter. For this reason DC link capacitors voltage balancing is crucial task in such configuration. The focus of this paper is a three-level three-phase neutral point clamped inverter. A modulation technique that balances the voltage in the DC link capacitors is presented. A Feedback voltage control method has been employed and a space vector pulse width modulation (SVPWM) is used as flexible technique to generate pulses that maintain a balanced DC link. The balancing is limited to an acceptable level without the use of the external active capacitor balancing circuit. To validate the effectiveness of the proposed method both simulation and experimental results are provided.