8-bits X 8-bits modified Booth 1’s complement multiplier

• Main Author: Norafiza Salehan
• Other Authors: Norina Idris (Advisor)
• Format: Learning Object
• Language: English
• Published: Universiti Malaysia Perlis 2008
• Subjects: Altera Quartus II; Multipliers; Very Large Scale Integration (VLSI); Carry Save Adder (CSA); Multipliers (Mathematical analysis)
• Online Access: http://dspace.unimap.edu.my/xmlui/handle/123456789/1934
• Institution: Universiti Malaysia Perlis

With advances in technology, many researchers have tried and are trying to design multipliers which offers either of following – high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier, thus making them suitable for various high speed...