The study of the effect of MOS transistor scaling on the critical device parameters

• Main Author: Zazurina Abd Rahman
• Other Authors: Ramzan Mat Ayub (Advisor)
• Format: Learning Object
• Language: English
• Published: Universiti Malaysia Perlis 2008
• Subjects: MOS transistor; Integrated circuits; Semiconductors; Metal oxide semiconductors; Metal oxide semiconductors > Mathematical models; Transistors; Metal oxide semiconductor field-effect transistors
• Online Access: http://dspace.unimap.edu.my/xmlui/handle/123456789/2342
• Institution: Universiti Malaysia Perlis

Since the invention of transistors some 30 years ago, CMOS devices have been scale down aggressively in each technology generations to achieve higher integration density and performance. The device shrinkage allow denser circuits, more functions per floor space, more complicated and integrated design, higher speed, lower supply voltage, which revolutionized the information and communication (ICT) technology. This report presents an investigation into the study of the effect of MOS transistor scaling on the critical device parameters. The parameters understudy are threshold voltage, on and off state leakage current, and short channel effect on sub-threshold characteristics, that have a direct influence on the integrated circuit (ICs) performance. An initial research found that, among the process parameters involved in the manufacture of devices, gate length has the most influential effect on those parameters. This study showed, for the MOSFET with gate length below one-tenths of a micrometer, has an operational problems. The study also proved that, producing MOSFET with channel lengths much smaller than a micrometer is a challenge, and the difficulties of semiconductor device fabrication are always a limiting factor in advancing integrated circuit technology.