SOI based nanowire single-electron transistors: design, simulation and process development
Link to publisher's homepage at http://www.unimap.edu.my/ ; Open access only applicable for vol. 1; issue 1, 2008.
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Universiti Malaysia Perlis
2008
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my.unimap-23832008-10-18T03:29:54Z SOI based nanowire single-electron transistors: design, simulation and process development Uda Hashim A. Rasmi Samsudi Sakrani Integrated circuits Silicon Transistors Nanostructured materials Single-electron transistors Integrated circuits -- Very large scale integration Link to publisher's homepage at http://www.unimap.edu.my/ ; Open access only applicable for vol. 1; issue 1, 2008. One of the great problems in current large-scale integrated circuits is increasing power dissipation in a small silicon chip. Single-electron transistors which operate by means of one-by-one electron transfer, is relatively small and consume very low power and suitable for achieving higher levels of integration. In this research, the four masks step are involved namely source and drain mask, Polysilicon gate mask, contact mask, and metal mask. The masks were designed using ELPHY Quantum GDS II Editor with a nanowire length and nanowire width of approximately 0.10μm and 0.010 μm respectively. In addition, the process flow development of SET and the process and device simulation of SET are also explained in this paper. The Synopsys TCAD simulation tools are utilized for process and device simulation. The results from the device simulation showed that the final SET was operating at room temperature (300K) with a capacitance estimated around 0.4297 aF. 2008-10-10T08:41:16Z 2008-10-10T08:41:16Z 2008 Article International Journal of Nanoelectronics and Materials, vol. 1 (1), 2008, pages 21-33. 1985-5761 (Printed) 1997-4434 (Online) http://www.unimap.edu.my http://hdl.handle.net/123456789/2383 en Universiti Malaysia Perlis |
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Integrated circuits Silicon Transistors Nanostructured materials Single-electron transistors Integrated circuits -- Very large scale integration |
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Integrated circuits Silicon Transistors Nanostructured materials Single-electron transistors Integrated circuits -- Very large scale integration Uda Hashim A. Rasmi Samsudi Sakrani SOI based nanowire single-electron transistors: design, simulation and process development |
| description |
Link to publisher's homepage at http://www.unimap.edu.my/ ; Open access only applicable for vol. 1; issue 1, 2008. |
| format |
Article |
| author |
Uda Hashim A. Rasmi Samsudi Sakrani |
| author_facet |
Uda Hashim A. Rasmi Samsudi Sakrani |
| author_sort |
Uda Hashim |
| title |
SOI based nanowire single-electron transistors: design, simulation and process development |
| title_short |
SOI based nanowire single-electron transistors: design, simulation and process development |
| title_full |
SOI based nanowire single-electron transistors: design, simulation and process development |
| title_fullStr |
SOI based nanowire single-electron transistors: design, simulation and process development |
| title_full_unstemmed |
SOI based nanowire single-electron transistors: design, simulation and process development |
| title_sort |
soi based nanowire single-electron transistors: design, simulation and process development |
| publisher |
Universiti Malaysia Perlis |
| publishDate |
2008 |
| url |
http://dspace.unimap.edu.my/xmlui/handle/123456789/2383 |
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1643787594588225536 |