The performance study of two genetic algorithm approaches for VLSI Macro-Cell layout area optimization
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Institute of Electrical and Electronics Engineering (IEEE)
2009
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my.unimap-68852017-11-29T04:45:08Z The performance study of two genetic algorithm approaches for VLSI Macro-Cell layout area optimization Hasliza, A. Rahim@Samsuddin Rahman, A. A A R. Badlishah, Ahmad Wan Nur Suryani Firuz, Wan Ariffin Muhammad Imran, Ahmad Integrated circuit layout Genetic algorithms Logic design Trees (mathematics) Very large scale integrated (VLSI) Circuit optimisation Integrated circuits Integrated circuits -- Design and construction Link to publisher's homepage at http://ieeexplore.ieee.org Very large scale integrated (VLSI) design has been the subject of much research since the early 1980s where the VLSI cell placement emerges to be a crucial stage in the chip design. Its area optimization is very important in order to reduce the delay and include more functionalities to the designed chip. The VLSI cell area optimization continues to become increasingly important to the performance of VLSI design due to the accelerating of the design complexities in VLSI. Thus, this paper addresses the performance comparisons of two different types of genetic algorithm (GA) techniques for VLSI macro-cell layout area optimization by utilizing the adopted method of cell placement that is binary tree method. Two GA approaches which are simple genetic algorithm (SGA) and steady-state genetic algorithm (SSGA) have been implemented and their performances in converging to their global minimums are examined and discussed. The performances of these techniques are tested on Microelectronics Center of North Carolina (MCNC) benchmark circuit's data set. The experimental results demonstrate that both algorithms achieve acceptable area requirement compared to the slicing floorplan approach (Lin et al., 2002). However, SSGA outperforms SGA where it achieves faster convergence rate and obtains more near optimum area. 2009-08-13T07:43:52Z 2009-08-13T07:43:52Z 2008 Article p.207-212 978-0-7695-3136-6 http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=4530477 http://hdl.handle.net/123456789/6885 en Proceedings of the 2nd Asia International Conference on Modeling & Simulation (AICMS 08) Institute of Electrical and Electronics Engineering (IEEE) |
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English |
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Integrated circuit layout Genetic algorithms Logic design Trees (mathematics) Very large scale integrated (VLSI) Circuit optimisation Integrated circuits Integrated circuits -- Design and construction |
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Integrated circuit layout Genetic algorithms Logic design Trees (mathematics) Very large scale integrated (VLSI) Circuit optimisation Integrated circuits Integrated circuits -- Design and construction Hasliza, A. Rahim@Samsuddin Rahman, A. A A R. Badlishah, Ahmad Wan Nur Suryani Firuz, Wan Ariffin Muhammad Imran, Ahmad The performance study of two genetic algorithm approaches for VLSI Macro-Cell layout area optimization |
| description |
Link to publisher's homepage at http://ieeexplore.ieee.org |
| format |
Article |
| author |
Hasliza, A. Rahim@Samsuddin Rahman, A. A A R. Badlishah, Ahmad Wan Nur Suryani Firuz, Wan Ariffin Muhammad Imran, Ahmad |
| author_facet |
Hasliza, A. Rahim@Samsuddin Rahman, A. A A R. Badlishah, Ahmad Wan Nur Suryani Firuz, Wan Ariffin Muhammad Imran, Ahmad |
| author_sort |
Hasliza, A. Rahim@Samsuddin |
| title |
The performance study of two genetic algorithm approaches for VLSI Macro-Cell layout area optimization |
| title_short |
The performance study of two genetic algorithm approaches for VLSI Macro-Cell layout area optimization |
| title_full |
The performance study of two genetic algorithm approaches for VLSI Macro-Cell layout area optimization |
| title_fullStr |
The performance study of two genetic algorithm approaches for VLSI Macro-Cell layout area optimization |
| title_full_unstemmed |
The performance study of two genetic algorithm approaches for VLSI Macro-Cell layout area optimization |
| title_sort |
performance study of two genetic algorithm approaches for vlsi macro-cell layout area optimization |
| publisher |
Institute of Electrical and Electronics Engineering (IEEE) |
| publishDate |
2009 |
| url |
http://dspace.unimap.edu.my/xmlui/handle/123456789/6885 |
| _version_ |
1643802700165414912 |