A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree

• Main Authors: Hasliza, A. Rahim@Samsuddin, Ab Al-Hadi, Ab Rahman, Andaljayalakshmi, G., R. Badlishah, Ahmad, Wan Nur Suryani Firuz, Wan Arrifin
• Other Authors: [e-mail]
• Format: Working Paper
• Language: English
• Published: Institute of Electrical and Electronics Engineers (IEEE) 2009
• Subjects: Integrated circuit layout; Integrated logic circuits; Trees (Mathematics); Genetic algorithms; VLSI; VLSI macro cell
• Online Access: http://dspace.unimap.edu.my/xmlui/handle/123456789/7406
• Institution: Universiti Malaysia Perlis

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