Design of FPGA based SPWM single phase inverter
MUCEET 2009 is organized by Malaysian Technical Universities Network (MTUN) comprising of Universiti Malaysia Perlis (UniMAP), Universiti Tun Hussein Onn (UTHM), Universiti Teknikal Melaka (UTeM) and Universiti Malaysia Pahang (UMP), 20th - 22nd June 2009 at M. S. Garden Hotel, Kuantan, Pahang.
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Universiti Malaysia Pahang (UMP)
2010
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my.unimap-86152010-08-12T04:22:39Z Design of FPGA based SPWM single phase inverter Afarulrazi, Abu Bakar Md Zarafi, Ahmad Farah Salwani, Abdullah Sinusoidal Pulse Width Modulation (SPWM) Field Programmable Logic Array (FPGA) Very High Description (VHDL) Malaysian Technical Universities Conference on Engineering and Technology (MUCEET) MUCEET 2009 is organized by Malaysian Technical Universities Network (MTUN) comprising of Universiti Malaysia Perlis (UniMAP), Universiti Tun Hussein Onn (UTHM), Universiti Teknikal Melaka (UTeM) and Universiti Malaysia Pahang (UMP), 20th - 22nd June 2009 at M. S. Garden Hotel, Kuantan, Pahang. Nowadays power inverter serves as an important emergency power supply system in events of mains power supply failure. The AC output voltage of a power electronic inverter is usually non-sinusoidal and hence has a high harmonic content. Sinusoidal Pulse Width Modulation (SPWM) scheme is normally used to convert the DC power supply into AC power supply by comparing the reference voltage waveform with the triangular waveform known as carrier. SPWM provides a way to reduce the total harmonic distortion of load current. The objective of this paper is to demonstrate a SPWM switching by using Altera DE2 board. In this SPWM, a sinusoidal reference voltage waveform is compared with the triangular carrier voltage to generate the on and off switching scheme. These switching schemes will trigger the gate of the power switch. In this paper, the SPWM switching strategies will be develop using Altera DE2 (Cyclone II EP2C35F672C6) with 16 bit serial configuration devices. The switching between reference and carrier waveforms of SPWM is obtained by using Matlab software. Simulation on the design pulses is conducted using Quartus II software tools provided by Altera. The output frequency of SPWM is 50 Hz and the design is limited to two levels of modulation index which are 0.5 and 0.75. 2010-08-12T04:22:39Z 2010-08-12T04:22:39Z 2009-06-20 Working Paper p.1-5 http://hdl.handle.net/123456789/8615 en Proceedings of the Malaysian Technical Universities Conference on Engineering and Technology (MUCEET) 2009 Universiti Malaysia Pahang (UMP) |
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Sinusoidal Pulse Width Modulation (SPWM) Field Programmable Logic Array (FPGA) Very High Description (VHDL) Malaysian Technical Universities Conference on Engineering and Technology (MUCEET) |
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Sinusoidal Pulse Width Modulation (SPWM) Field Programmable Logic Array (FPGA) Very High Description (VHDL) Malaysian Technical Universities Conference on Engineering and Technology (MUCEET) Afarulrazi, Abu Bakar Md Zarafi, Ahmad Farah Salwani, Abdullah Design of FPGA based SPWM single phase inverter |
| description |
MUCEET 2009 is organized by Malaysian Technical Universities Network (MTUN) comprising of Universiti Malaysia Perlis (UniMAP), Universiti Tun Hussein Onn (UTHM), Universiti Teknikal Melaka (UTeM) and Universiti Malaysia Pahang (UMP), 20th - 22nd June 2009 at M. S. Garden Hotel, Kuantan, Pahang. |
| format |
Working Paper |
| author |
Afarulrazi, Abu Bakar Md Zarafi, Ahmad Farah Salwani, Abdullah |
| author_facet |
Afarulrazi, Abu Bakar Md Zarafi, Ahmad Farah Salwani, Abdullah |
| author_sort |
Afarulrazi, Abu Bakar |
| title |
Design of FPGA based SPWM single phase inverter |
| title_short |
Design of FPGA based SPWM single phase inverter |
| title_full |
Design of FPGA based SPWM single phase inverter |
| title_fullStr |
Design of FPGA based SPWM single phase inverter |
| title_full_unstemmed |
Design of FPGA based SPWM single phase inverter |
| title_sort |
design of fpga based spwm single phase inverter |
| publisher |
Universiti Malaysia Pahang (UMP) |
| publishDate |
2010 |
| url |
http://dspace.unimap.edu.my/xmlui/handle/123456789/8615 |
| _version_ |
1643789269579333632 |