High efficiency 2.4 GHz CMOS two stages class-F power amplifier for wireless transmitters
A design of CMOS class-F power amplifier (PA) at 2.4-GHz for wireless transmitters is presented. The class-F PA design is implemented by using 0.13-μm CMOS process. The proposed class-F PA employs cascade topology. The transistor’s on resistance is decreased by designing the transistors in parallel....
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| Main Authors: | , , , |
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| Format: | E-Article |
| Published: |
Bentham Science Publishers B.V.
2016
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| Subjects: | |
| Online Access: | http://ir.unimas.my/id/eprint/12508/ https://www.scopus.com/inward/record.uri?eid=2-s2.0-84966373190&partnerID=40&md5=8daf3962fe313ac51f8fa2db0f94173b |
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| Institution: | Universiti Malaysia Sarawak |
| Summary: | A design of CMOS class-F power amplifier (PA) at 2.4-GHz for wireless transmitters is presented. The class-F PA design is implemented by using 0.13-μm CMOS process. The proposed class-F PA employs cascade topology. The transistor’s on resistance is decreased by designing the transistors in parallel. Therefore, the efficiency is increased. The first stage is a common-source driver stage is biased in a class-AB to provide sufficient input voltage swing for the amplifier stage, while the amplifier stage is biased in cut-off region. Therefore, the transistor can operate as a switching-mode for high efficiency. The simulation results show that the power added efficiency (PAE) of 60% is obtained at 1.3 V power supply and the PA delivers 12 dBm output power. The chip area is 0.66 mm2. |
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