A Linear-in-decibel RF Power Detector for Microwave Measurements in the S-band Frequency using CMOS Technology
This paper investigates the implementation and design of a low-power linear-in-decibel RF power detector using a 180-nm standard CMOS process for applications in the S-band frequency. The proposed circuit aims at applications in wireless communication and as sensing devices in the agricultural secto...
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| Main Authors: | , , , |
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| Format: | Proceeding |
| Language: | English |
| Published: |
2021
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| Subjects: | |
| Online Access: | http://ir.unimas.my/id/eprint/39150/3/A%20Linear%20-%20Copy.pdf http://ir.unimas.my/id/eprint/39150/ https://ieeexplore.ieee.org/document/9623225 |
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| Institution: | Universiti Malaysia Sarawak |
| Language: | English |
| Summary: | This paper investigates the implementation and design of a low-power linear-in-decibel RF power detector using a 180-nm standard CMOS process for applications in the S-band frequency. The proposed circuit aims at applications in wireless communication and as sensing devices in the agricultural sector. A logarithmic amplifier is employed to achieve wide dynamic range linear-in-decibel output. A current-source-load RMS power detector is placed before the logarithmic amplifier to improve the RF power detector sensitivity. MOSFETS square-law principle in the saturation region is exploited to perform power detection. The logarithmic amplifier is realized using five identical differential limiting amplifiers, amplifying and compressing the wide dynamic range input signal. Each limiting amplifier is designed as 11.2 dB gain cells. The circuit is designed and simulated using 180-nm CMOS process parameters. The simulation results demonstrate that the RF power detector can detect power from −50 dBm to 0 dBm. The power detector operating frequency is from 2 GHz to 4 GHz, and its supply voltage is 1.8 V. The total power dissipation is 0.610 mW. |
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