Area Optimization for Networks-on-Chip Architectures using Deep Network Partitioning

• Main Authors: Asrani, Lit, Hazrul, Mohamed Basri, M. N., Marsono, S. N. S., Hussin, Yee, O. C.
• Format: Proceeding
• Language: English
• Published: 2011
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://ir.unimas.my/id/eprint/41637/3/Area%20Optimization.pdf; http://ir.unimas.my/id/eprint/41637/
• Institution: Universiti Malaysia Sarawak

This paper presents an area optimization for Network-on-Chip (NoC) architecture using deep Network Par- titioning technique. Among the hardest problems in NoC design is customizing the topological structure and application mapping on on-chip network in order to cater for application demand at minimal cost. The area cost of NoC is cut down by utilizing multi- level network partitioning where it partitions large networks into smaller segments. The enhancement in area cost is obtained by reducing both router area and the number of global links. In terms of performance, the multi-level network partitioning offers a better solution by assigning computational cores with heavy inter-core communications into the same segment. Therefore, the average inter-node distances would be minimized. This directly results in better performance due to its shortest path. For verification, the proposed technique has been tested on various System-on-Chip (SoC) applications case studies. The proposed technique results in the reduction of more than 7% router area, 19% global links, and 12% average inter-node distance.