Delay Aware Topology Generation for Network on Chip
Network-on-Chip (NoC) is a scalable bandwidth requirement that using on-chip packet-switched micro-network of interconnects. NoC are based on System-on-Chips(SoCs) that traditionally large-scale multi-processors and distributed computing networks. The NoC performances analysis were evaluated in term...
Saved in:
| Main Authors: | , , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
LAP LAMBERT Academic Publishing
2015
|
| Subjects: | |
| Online Access: | http://ir.unimas.my/id/eprint/41659/1/Delay%20Aware%20Topology.pdf http://ir.unimas.my/id/eprint/41659/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Institution: | Universiti Malaysia Sarawak |
| Language: | English |