VHDL implementation for measurement of the distance test distribution pattern of the Tri-Axial magnetic probe for the PD detection circuit system by using 3 GHz ADC and FPGA

• Main Authors: Emilliano, Chakrabarty C.K., Ghani A.B.A., Ramasamy A.K.
• Other Authors: 35974769600
• Format: Conference paper
• Published: 2023
• Subjects: 64 Bit BCD Counter with Reset Block; 64 Bit Latch Block; ADC with Peak Detector Block; FPGA Simulation; FPGA Technology; Partial Discharge Detection; Real Time Processing; Reset Automatic Block; Underground Cable; VHDL Programming; Cables; Computer hardware description languages; Detectors; Exhibitions; Field programmable gate arrays (FPGA); Partial discharges; Probes; Technology; Underground cables; FPGA technology; Partial discharge detection; Peak detectors; Realtime processing; Signal detection
• Institution: Universiti Tenaga Nasional

This paper is purely a model to implement Partial Discharge (PD) detection in FPGA technology and then implement the VHDL modeled in FPGA technology for measurement of the distance test distribution pattern of the Tri-Axial magnetic probe using 3GHz ADC (ADC083000RB-Reference Board) and impulse gene...