MATLAB and VHDL model of real time partial discharge detection using FPGA technology

• Main Authors: Emilliano, Chakrabarty C.K., Ramasamy A.K., Ghani A.B.A.
• Other Authors: 35974769600
• Format: Conference paper
• Published: 2023
• Subjects: 64 Bits BCD Counter with Reset Block; ADC with Peak Detector Block; FPGA Simulation; FPGA Technology; MATLAB Model; Partial Discharge Detection; Underground Cable; VHDL Model; Cables; Detectors; Partial discharges; Real time systems; Signal detection; Underground cables; FPGA technology; Peak detectors; VHDL-model; MATLAB
• Institution: Universiti Tenaga Nasional

This research involves evaluating the use of FPGA for the detection and counting of partial discharge (PD) signals in underground cables (XLPE cables). PD detection model was designed one using MATLAB and another using VHDL. The pulse signal from the cable was processed and counted using peak detect...