FPGA simulation of AD converter by using Giga Hertz speed data acquisition for partial discharge detection

• Main Authors: Emilliano, Chakrabarty C.K., Basri A., Ramasamy A.K., Ping L.C.
• Other Authors: 35974769600
• Format: Article
• Published: 2023
• Subjects: ADC with peak detector block; Counter with reset block; FPGA simulation; FPGA technology; Partial discharge detection; Real time processing; Underground cable; VHDL programming
• Institution: Universiti Tenaga Nasional

Currently, FPGA (Field Programmable Gate Array) technology is being widely used for accelerator control owing to its fast digital processing capability. This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall i...