VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA

• Main Authors: Emilliano, Chakrabarty, C.K., Ghani, A.B.A., Ramasamy, A.K.
• Format: Conference Paper
• Language: en_US
• Published: 2017
• Institution: Universiti Tenaga Nasional

This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST) using Very high integrated circuit Hardware Description Language...