Failure Analysis Investigation on 2N7002LTI TMOS Device Due to Electrostatic Discharge (ESD) Failures

• Main Author: Abdul Manaf, Abdul Halim
• Format: Thesis
• Language: English; English
• Published: 1998
• Online Access: http://psasir.upm.edu.my/id/eprint/10121/1/FK_1998_5_A.pdf; http://psasir.upm.edu.my/id/eprint/10121/
• Institution: Universiti Putra Malaysia

The common failures in the electronic devices e.g. Metal Oxide Semiconductor(MOS), and T type Metal Oxide Semiconductor Field Effect Transistor (TMOS) are due to Electrostatic Discharge(ESD) and Electrical Overseers(EOS). A review is carried out giving an account of various types of failures and failure analysis philosophies. investigation. methodology developed here, Seremban, between Gate to Source(BVGSS) Stress Test, Parametric Abnormality Test (PA T) to induce failure. It h as been observed that the 2N7002LTl lMOS device does not fail within 45 volts of positively as well as negatively biased voltage condition when applied to the gate and source of the device, during BVGSS Stress Test. On the other hand the Voltage Susceptibility Test has given a limiting voltage of 110 volts, for the device to fail. The failure of the devices have been studied using the failure analysis philosophy developed here and it is observed that the failure is due to thinning of the gate oxide layer. The detailed scanning electron microscope (SEM) study has been carried out to comment on the additional mechanics of failure. The amount thinning of the gate oxide layer in the various regions of the device has been found to be in the range of 800 to 950 Angstroms.