Optimality of bus-invert coding
Dynamic power dissipation on I/O buses is an important issue for high-speed communication between chips. One can use coding techniques to reduce the number of transitions, which will reduce the dynamic power. Bus-invert coding is one popular technique for interchip buses, where the dominant contribu...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English English |
| Published: |
Institute of Electrical and Electronics Engineers Inc.
2009
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| Online Access: | http://psasir.upm.edu.my/id/eprint/15953/1/Optimality%20of%20bus.pdf http://psasir.upm.edu.my/id/eprint/15953/ |
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| Institution: | Universiti Putra Malaysia |
| Language: | English English |
| Summary: | Dynamic power dissipation on I/O buses is an important issue for high-speed communication between chips. One can use coding techniques to reduce the number of transitions, which will reduce the dynamic power. Bus-invert coding is one popular technique for interchip buses, where the dominant contribution is from the self-capacitance of the wires. This algorithm uses an invert line to signal whether the bus data are in its original or an inverted form. While the method appears to be a greedy algorithm, we show that it is, in fact, an optimal strategy. To do so, we first represent the bus and invert line using a trellis diagram. Then, we show that applying bus-invert coding to a sequence of words gives the same result as would be obtained by using the Viterbi algorithm, which is known to be optimal. We also show that partitioning an M-bit bus into P subbuses and using bus-invert coding on each subbus can be described as applying the Viterbi algorithm on a 2P-state trellis. |
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