A procedure of a test pattern generation for CMOS operational amplifier based on the inverting amplifier

• Main Authors: Abdul Halin, Izhal, Suparjo, Bambang Sunaryo, Wan Hasan, Wan Zuha, Wagiran, Rahman, Mohd Sidek, Roslina
• Format: Conference or Workshop Item
• Language: English
• Published: Universiti Putra Malaysia Press 2002
• Online Access: http://psasir.upm.edu.my/id/eprint/18388/1/18388.pdf; http://psasir.upm.edu.my/id/eprint/18388/
• Institution: Universiti Putra Malaysia

The microchip, an ultra-small and fragile electrical system is prone to damage either during the fabrication process or during the operation of the device itself. In microchip production, the final products are all identical because a master mold is used for production. This also implies that there is a large possibility that defects of all the products are also the same in nature. If the cause and location of damage in a microchip is identified before mass production, it could be prevented. In order to do so, tests have to be done. Unlike in Digital Design, Test Pattern Generation (TPG) in Analog Design is still new. This paper discussed a developed procedure to generate a Test Pattern for a CMOS Operational Amplifier (Op-Amp) using an Inverting Amplifier that consists of the Device Under Test (Dl)T) which is the Op-Amp. The work includes designing an Op-Amp, applying the Op-Amp as an Inverting Amplifier, modeling the faults and finally generating a Test Pattern. Relevant figures, graphs and tables obtained from computer simulation presented in this paper will foster better understanding of the procedure developed. This paper argues that if the developed procedure is incorporated in the production sequence of Op-Amp Integrated Circuits (IC), quality standards of the Op-Amps produced are certainly to be elevated.