Optimising built-in-self-test using K-map LFSR on parallel multiplier circuit

• Main Authors: Wan Hasan, Wan Zuha, Ali, Mohd Liakot, Romli, Norfazliana
• Format: Conference or Workshop Item
• Language: English
• Published: 2002
• Online Access: http://psasir.upm.edu.my/id/eprint/18394/1/18394.pdf; http://psasir.upm.edu.my/id/eprint/18394/
• Institution: Universiti Putra Malaysia

Current trend in Integrated Circuits (IC) implementation such as System-on-Chip (SOC) has contributed significant advantages in electronic product features such as high circuit performance with high number of functions, small physical area and high reliability. Therefore, including Built-In-Self-Test (BIST) facility into each subsystem of SOC is considered a good solution. Commonly, BIST structure is based on random test data generation from a Linear Feedback Shift Register (LFSR) due to its simple, small and economical circuit structure. For this reason, development of test pattern" for BIST based on combination of K-map LFSR and deterministic approach could provide one of the solutions to reduce the testing time. This paper describes the test efficiencies based on combination of K-map LFSR features and deterministic test pattern. A parallel multiplier that considered as one of the demanding subsystems is chosen to verify the proposed BIST performance.