Area efficient test circuit for library standard cell qualification

• Main Authors: Al-Frajat, Jaafar Khadair Kadam, Flayyih, Wameedh Nazar, Mohd Sidek, Roslina, Samsudin, Khairulmizam, Rokhani, Fakhrul Zaman
• Format: Conference or Workshop Item
• Language: English
• Published: IEEE 2015
• Online Access: http://psasir.upm.edu.my/id/eprint/2848/1/Area%20efficient%20test%20circuit%20for%20library%20standard%20cell%20qualification.pdf; http://psasir.upm.edu.my/id/eprint/2848/
• Institution: Universiti Putra Malaysia

High cost of qualifying library standard cells on silicon wafer limits the number of test circuits on the test chip. This paper proposes a technique to share common load circuits among test circuits to reduce the silicon area. By enabling the load sharing, number of transistors for the common load c...