Analysis and modeling of ASIC area at early-stage design for standard cell library selection
Area-delay curve is an effective technique to compare and select the appropriate library at different target delay constraint. However, generating area-delay curve requires time-consuming synthesis processes. This paper presents a fast area estimation model to allow the designer to select the optima...
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| Main Authors: | , , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2019
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| Online Access: | http://psasir.upm.edu.my/id/eprint/36345/1/Analysis%20and%20modeling%20of%20ASIC%20area%20at%20early-stage%20design%20for%20standard%20cell%20library%20selection.pdf http://psasir.upm.edu.my/id/eprint/36345/ |
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| Institution: | Universiti Putra Malaysia |
| Language: | English |
| Summary: | Area-delay curve is an effective technique to compare and select the appropriate library at different target delay constraint. However, generating area-delay curve requires time-consuming synthesis processes. This paper presents a fast area estimation model to allow the designer to select the optimal library for designing area-optimized circuit. The model predicts the area-delay curves for a target circuit based on reduced number of synthesis performed at different frequencies. As compared to the general linear search method, the proposed model with 5 synthesis points results 16.5X-18.6X runtime reduction with average error of 2.74%~5.74% in different height libraries implementation. This shows that the proposed model is beneficial for area optimal library selection at the early stage of design. |
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