Design of a reconfigurable FFT processor using multi-objective genetic algorithm
This paper describes the implementation of Multi-objective Genetic Algorithm (MOGA) in a 16-point Radix-4 Single Path Delay Feedback (R4SDF) pipelined Fast Fourier Transform (FFT) processor in Verilog. The role of MOGA is to optimize the wordlength of the FFT coefficient and at the same time make su...
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| Main Authors: | , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2010
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| Online Access: | http://psasir.upm.edu.my/id/eprint/47776/1/Design%20of%20a%20reconfigurable%20FFT%20processor%20using%20multi-objective%20genetic%20algorithm.pdf http://psasir.upm.edu.my/id/eprint/47776/ |
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| Institution: | Universiti Putra Malaysia |
| Language: | English |
| Summary: | This paper describes the implementation of Multi-objective Genetic Algorithm (MOGA) in a 16-point Radix-4 Single Path Delay Feedback (R4SDF) pipelined Fast Fourier Transform (FFT) processor in Verilog. The role of MOGA is to optimize the wordlength of the FFT coefficient and at the same time make sure the processor operates at acceptable Signal to Noise Ratio (SNR). Reducing the wordlength of FFT coefficient will contribute to lower Switching Activity (SA), thus lower power consumption is required for the operation of FFT processor. |
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