A low power multiplexer based pass transistor logic full adder

• Main Authors: Kamsani, Noor Ain, Thangasamy, Veeraiyah, Hashim, Shaiful Jahari, Yusoff, Zubaida, Bukhori, Muhammad Faiz, Hamidon, Mohd Nizar
• Format: Conference or Workshop Item
• Language: English
• Published: IEEE 2015
• Online Access: http://psasir.upm.edu.my/id/eprint/56112/1/A%20low%20power%20multiplexer%20based%20pass%20transistor%20logic%20full%20adder.pdf; http://psasir.upm.edu.my/id/eprint/56112/
• Institution: Universiti Putra Malaysia

In this paper, a high-speed low-power full adder design using multiplexer based pass transistor logic featuring full-swing output is proposed. The adder is designed and simulated using the industry standard 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 29×10-18 J and its power consumption is 2.01μW. The proposed full adder is also capable to function at lower supply voltages of 0.4 V and 0.8 V without significant performance degradation. The proposed adder when cascaded in a 4-bit ripple carry adder configuration, its power, delay and PDP performance are better than the other adders making it suitable for larger arithmetic circuits.