New tool for converting high-level representations of finite state machines to verilog HDL
Automated conversion of high-level representation of Finite State Machine (FSM) to correct-by-construction Hardware Description Language (HDL) is of demand with the increasing complexity of the modern digital controller designs. In this paper, we proposed a tool implementing systematic methodology f...
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| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2017
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| Online Access: | http://psasir.upm.edu.my/id/eprint/59460/1/New%20tool%20for%20converting%20high-level%20representations%20of%20finite%20state%20machines%20to%20verilog%20HDL.pdf http://psasir.upm.edu.my/id/eprint/59460/ |
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| Institution: | Universiti Putra Malaysia |
| Language: | English |