Enhanced control algorithms for multilevel inverter-based shunt active power filter

• Main Author: Hoon, Yap
• Format: Thesis
• Language: English
• Published: 2017
• Online Access: http://psasir.upm.edu.my/id/eprint/71222/1/FK%202017%2080%20-%20IR.pdf; http://psasir.upm.edu.my/id/eprint/71222/
• Institution: Universiti Putra Malaysia

Nowadays, harmonics mitigations and reactive power compensations are compulsory in power distribution systems due primarily to significant increment of current harmonics and reactive power burden resulted from widespread applications of power electronic devices. Among the existing mitigation solutions, multilevel inverter-based shunt active power filter (SAPF) is potentially to be effective against current harmonics and power factor (PF) degradation, and its mitigation performance is strictly dependent on the quality of its control algorithms. In this work, three main problems were identified for further investigation. First, dependency on current control algorithm alone is insufficient to solve the severe inherent voltage imbalance problems of multilevel inverters. Second, overall DC-link voltage of SAPF is still regulated using inaccurate yet slow response control algorithms. Third, the existing harmonics extraction algorithms are still exhibiting significant time delay and possessing redundant features. Therefore, the main aim of this work is to develop new control algorithms which are capable of improving mitigation and dynamic performances of three-level neutralpoint diode clamped (NPC) inverter-based SAPF. Specifically, this work focuses on three main control algorithms. Firstly, a simple fuzzy-based dwell time allocation (FDTA) control technique is formulated to enhance the performance of space vector pulse-width modulation (SVPWM) current control algorithm in minimizing inherent voltage imbalance problems of three-level NPC inverter, by suitably adjusting the dwell time of each designated switching state in response to voltage imbalance of DC-link capacitors. Next, a unique inverted error deviation (IED) control technique is incorporated into the main DC-link capacitor voltage regulation algorithm. By utilizing indirect voltage error manipulation approach with reduced computational efforts, the overall DC-link voltage of SAPF is efficiently controlled. Lastly, a new current harmonics extraction algorithm known as simplified synchronous reference frame (SSRF) algorithm is developed, and with its simplified features, it is able to respond quickly to various system conditions while maintaining high accuracy. SAPF with all the proposed control algorithms is developed and evaluated in MATLAB-Simulink involving various highly nonlinear rectifier loads. In addition, it is thoroughly evaluated under both steady-state and dynamic-state conditions. Moreover, a laboratory prototype is developed with all the proposed control algorithms downloaded in TMS320F28335 digital signal processor (DSP) board for validation purposes. From the findings, by incorporating advantages of the proposed FDTA technique, voltages across all the DC-link capacitors are found to be equal, thereby achieving voltage balancing. Without FDTA technique, SVPWM current control algorithm fails to maintain voltage balance of all the DC-link capacitors. Meanwhile, the proposed DC-link capacitor voltage regulation algorithm with IED control technique performs with high accuracy, which is in the range of 99.96 % to 100 %, and fast response time, which is within 0.20 s. Next, by utilizing the proposed SSRF algorithm, SAPF is observed to perform outstandingly with low THD values, which is in the range of 0.96 % to 3.28 % and fast response time, which is within 0.025 s. Finally, mitigation performance of the three-level NPC inverter-based SAPF while using all the proposed control algorithms simultaneously (Set 3) is observed to be the best.