Formal Verification of Logic Control Systems with Nondeterministic Behaviors
This paper describes a formal modeling and verification of an arm pick-and-place system, in which nondeterministic behaviors of the arm state condition and timer function blocks are applied. We design an appropriate PLC program using a ladder diagram (LD) for the arm pick-and-place operation and app...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
The Institute of Electrical Engineers of Japan
2013
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| Subjects: | |
| Online Access: | http://eprints.utem.edu.my/id/eprint/11248/1/_pdf http://eprints.utem.edu.my/id/eprint/11248/ https://www.jstage.jst.go.jp/article/ieejjia/2/6/2_306/_article |
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| Institution: | Universiti Teknikal Malaysia Melaka |
| Language: | English |