Elliptic-curve cryptographic architectures for system-on-chip based on field programmable gate arrays
Elliptic curve cryptography (ECC) is an alternative mechanism for implementing public-key cryptographic system. The main reason for the attractiveness of ECC in data security systems is the fact that significantly smaller parameters are needed as compared to other competitive systems, but with equiv...
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Main Author: | |
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Format: | Thesis |
Language: | English |
Published: |
2009
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Subjects: | |
Online Access: | http://eprints.utm.my/id/eprint/12691/1/ArifIrwansyahMFKE2009.pdf http://eprints.utm.my/id/eprint/12691/ |
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Institution: | Universiti Teknologi Malaysia |
Language: | English |
Summary: | Elliptic curve cryptography (ECC) is an alternative mechanism for implementing public-key cryptographic system. The main reason for the attractiveness of ECC in data security systems is the fact that significantly smaller parameters are needed as compared to other competitive systems, but with equivalent levels of security. This thesis presents the design exploration of elliptic-curve cryptographic architectures for Field Programmable Gate Arrays (FPGA)-based System-on-Chip (SoC). The architectures explored include tightly-coupled custom logic and loosely-coupled coprocessor. The ECC hardware is designed and parameterized for key sizes of 163, 193, and 233 bits. The designs are described in Verilog and VHDL. A demonstration application prototype is developed in which an Elliptic Curve Digital Signature Algorithm (ECDSA) system is combined with a hybrid encryption cryptosystem in one SoC implementation. This application prototype is used in the verification of the designs. Experimental results show that, while utilizing less logic, tightly-coupled architecture improves the execution time of point multiplication operation by about 50% as compared to the loosely-coupled coprocessor. For point addition operation execution time, the tightly-coupled architecture offers 56% improvement as compared to the loosely-coupled coprocessor. The benchmarking of the design with other existing ECC tightly coupled hardwares shows that the design is about fourteen times faster in terms of clock cycles. |
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