Analysis and performance evaluation of a fault-tolerant multistage interconnection network

A single error occurs in the non fault-tolerant Multistage Interconnection Networks (MINs) render a catastrophe to the MINs. The new scheme is to design a fault-tolerant MIN. Multiple paths between an input port and output port in the proposed network are established by chaining switching elements w...

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Main Author: Hui, Seng Kheong
Format: Thesis
Language:English
Published: 2003
Subjects:
Online Access:http://eprints.utm.my/id/eprint/42579/1/HuiSengKheongFKE2003.pdf
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Institution: Universiti Teknologi Malaysia
Language: English
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spelling my.utm.425792017-10-17T10:46:17Z http://eprints.utm.my/id/eprint/42579/ Analysis and performance evaluation of a fault-tolerant multistage interconnection network Hui, Seng Kheong TK Electrical engineering. Electronics Nuclear engineering A single error occurs in the non fault-tolerant Multistage Interconnection Networks (MINs) render a catastrophe to the MINs. The new scheme is to design a fault-tolerant MIN. Multiple paths between an input port and output port in the proposed network are established by chaining switching elements which have the same partition in the same stage. To enhance the performance and reliability of the proposed switch, sub-switches are straddled across the stages in the proposed network. This thesis examines the performance and design issues of fault-tolerant MINs. It first presents a survey of the current state of the art in MINs. Then, it investigates one of the most important design issues: cost-effectiveness. Following this comprehensive study, the thesis proposed a fault-tolerant MIN model. Analytical models for evaluation of the proposed network survivability and performance are presented. Finally the thesis presents fault-diagnosis methods to locate possible single fault occurs in the proposed network. Because maximum alternatives paths in the network are exploited, the proposed fault-tolerant switch has long lifetime and high bandwidth. Compared to other switches, it performs better in term of cost-effectiveness and throughput. In conclusion, we have successfully developed a fault-tolerant MIN which is: high survivability, simple control algorithm, full connecting capability and high bandwidth. 2003 Thesis NonPeerReviewed application/pdf en http://eprints.utm.my/id/eprint/42579/1/HuiSengKheongFKE2003.pdf Hui, Seng Kheong (2003) Analysis and performance evaluation of a fault-tolerant multistage interconnection network. PhD thesis, Universiti Teknologi Malaysia, Faculty of Computing. http://libraryopac.utm.my/client/en_AU/main/search/results?qu=Analysis+and+performance+evaluation+of+a+fault-tolerant+multistage+interconnection+network&te=
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
language English
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Hui, Seng Kheong
Analysis and performance evaluation of a fault-tolerant multistage interconnection network
description A single error occurs in the non fault-tolerant Multistage Interconnection Networks (MINs) render a catastrophe to the MINs. The new scheme is to design a fault-tolerant MIN. Multiple paths between an input port and output port in the proposed network are established by chaining switching elements which have the same partition in the same stage. To enhance the performance and reliability of the proposed switch, sub-switches are straddled across the stages in the proposed network. This thesis examines the performance and design issues of fault-tolerant MINs. It first presents a survey of the current state of the art in MINs. Then, it investigates one of the most important design issues: cost-effectiveness. Following this comprehensive study, the thesis proposed a fault-tolerant MIN model. Analytical models for evaluation of the proposed network survivability and performance are presented. Finally the thesis presents fault-diagnosis methods to locate possible single fault occurs in the proposed network. Because maximum alternatives paths in the network are exploited, the proposed fault-tolerant switch has long lifetime and high bandwidth. Compared to other switches, it performs better in term of cost-effectiveness and throughput. In conclusion, we have successfully developed a fault-tolerant MIN which is: high survivability, simple control algorithm, full connecting capability and high bandwidth.
format Thesis
author Hui, Seng Kheong
author_facet Hui, Seng Kheong
author_sort Hui, Seng Kheong
title Analysis and performance evaluation of a fault-tolerant multistage interconnection network
title_short Analysis and performance evaluation of a fault-tolerant multistage interconnection network
title_full Analysis and performance evaluation of a fault-tolerant multistage interconnection network
title_fullStr Analysis and performance evaluation of a fault-tolerant multistage interconnection network
title_full_unstemmed Analysis and performance evaluation of a fault-tolerant multistage interconnection network
title_sort analysis and performance evaluation of a fault-tolerant multistage interconnection network
publishDate 2003
url http://eprints.utm.my/id/eprint/42579/1/HuiSengKheongFKE2003.pdf
http://eprints.utm.my/id/eprint/42579/
http://libraryopac.utm.my/client/en_AU/main/search/results?qu=Analysis+and+performance+evaluation+of+a+fault-tolerant+multistage+interconnection+network&te=
_version_ 1643650936960188416