Systematic tuning procedure for analog design reuse methodology

• Main Author: Adnan, Ahmad Faisal
• Format: Thesis
• Language: English
• Published: 2014
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/50681/25/AhmadFaisalAdnanMFKE2014.pdf; http://eprints.utm.my/id/eprint/50681/
• Institution: Universiti Teknologi Malaysia

Shrinking transistor is undeniably important especially to reduce fabrication cost and to increase power efficiency of electronic devices. However, as fabrication technology progresses into deep submicron process, analog circuit design complexity grows significantly together with the increase in design time due to complex behaviour of short-channel Metal-Oxide-Semiconductor (MOS) transistor. Current scaling rules are incapable of maintaining circuit performance as design technology moves to deep submicron process. This research carries out a study on the effects of fabrication process migration on analog design reuse approach and offers a complementary design solution. In order to prove the concept, two-stage Operational Transconductance Amplifiers (OTA) have been designed using Silterra 0.18 µm Complimentary-MOS (CMOS) fabrication process and were later migrated to Silterra 0.13 µm. Existing scaling rules were adopted in the study in order to maintain the original circuit performance in 0.18 µm process. The performance degradation problems due to the migration into a deep submicron process were observed. Then, a solid-state systematic transistor tuning procedure based on Direct Current (DC) output scaling rule was proposed and applied to rectify the performance degradation problem due to design migration. Result shows that it improves the accuracy of the analog design scaling and can be applied to both short-channel and long-channel designs. On a Miller amplifier test circuit, the proposed tuning stage results in an additional voltage gain up to 16 dB and twice faster settling time compared to a single-stage scaling alone, and approximately 33% less power consumption and 28% smaller silicon area when compared to the original design on 0.18 µm process. The research is expected to contribute to current development of analog design reuse methodology.