Zero-delay FPGA-based odd-even sorting network

• Main Authors: Hematian, Amirshahram, Chuprat, Suriayati, Manaf, Azizah Abdul, Parsazadeh, Nadia
• Format: Conference or Workshop Item
• Published: 2013
• Subjects: QA75 Electronic computers. Computer science
• Online Access: http://eprints.utm.my/id/eprint/51402/; http://dx.doi.org/10.1007/978-3-642-37371-8_23
• Institution: Universiti Teknologi Malaysia

Sorting is one of the most well-known problems in computer science and is frequently used for benchmarking computer systems. It can contribute significantly to the overall execution time of a process in a computer system. Dedicated sorting architectures can be used to accelerate applications and/or to reduce energy consumption. In this paper, we propose an efficient sorting network aiming at accelerating the sorting operation in FPGA-based embedded systems. The proposed sorting network is implemented based on an Optimized Odd-even sorting method (O-2) using fully pipelined combinational logic architecture and ring shape processing. Consequently, (O-2) generates the sorted array of numbers in parallel when the input array of numbers is given, without any delay or lag. Unlike conventional sorting networks, (O-2) sorting network does not need memory to hold data and information about sorting, and neither need input clock to perform the sorting operations sequentially. We conclude that by using (O-2) in FPGA-based image processing, we can optimize the performance of filters such as median filter which demands high performance sorting operations for real-time applications.