SVA checker generator for FPGA-based verification platform

• Main Authors: Mohamad, N., Ooi, C. Y., Ismail, N., Teh, J.
• Format: Conference or Workshop Item
• Published: Institute of Electrical and Electronics Engineers Inc. 2016
• Subjects: T Technology (General)
• Online Access: http://eprints.utm.my/id/eprint/73107/; https://www.scopus.com/inward/record.uri?eid=2-s2.0-84983454978&doi=10.1109%2fISCAS.2016.7538906&partnerID=40&md5=43d58ebd2bdf919b41e242ce9a460a05
• Institution: Universiti Teknologi Malaysia

This paper discusses development of FPGA-based verification platform which consists of System' Verilog assertion (SVA) checker generator to synthesize SVA into Verilog code. We derive a lookup table that consists of SVA operators and their corresponding synthesizable RTL coding. Assertion check...