Enhancing fault tolerance and reducing delay in virtual network embedding using NSGA-II

• Main Authors: Bansal, A., Kaiwartya, O., Singh, R. K., Prakash, S.
• Format: Conference or Workshop Item
• Published: Institute of Electrical and Electronics Engineers Inc. 2016
• Subjects: QA75 Electronic computers. Computer science
• Online Access: http://eprints.utm.my/id/eprint/73475/; https://www.scopus.com/inward/record.uri?eid=2-s2.0-84962866451&doi=10.1109%2fIC4.2015.7375703&partnerID=40&md5=0e67beddd4ee0833aac013f6a8b4224e
• Institution: Universiti Teknologi Malaysia

To improve utilization of resources, efficient resource sharing technique is the key requirement. Recently, Virtual Network Embedding (VNE) has been explored as a resource sharing technique for the modern Internet architecture. The VNE techniques suggested in literature, fault tolerance of connections and nodes of network has not been taken into account. Therefore, these techniques improve resource utilization but their performance is not reliable in realistic network scenario considering the presence of failure in real network environment. To incorporate fault tolerance into account while designing VNE technique, this paper proposes a method for enhancing fault tolerance and reducing delay using Non-dominated Sorting based Genetic Algorithm (NSGA-II). A multi-objective optimization problem is mathematically derived. The two objectives of the optimization problem are fault tolerance and delay of a network path. Modified NSGA-II is developed to solve the optimization problem. Analysis of simulation results confirms that M-NSGA-II effectively optimizes both the objectives of the problem of VNE.