Implementation of harris corner detector on fpga
Harris Corner Detector (HCD) algorithm is widely used in many applications of image processing. Its performance with noisy images exceeds many other methods, in terms of accuracy and stability. Various methods are used to compare images and detect moving objects such as block matching but these meth...
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis |
| Language: | English |
| Published: |
2016
|
| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/81604/1/MohammedOmarAwadhMFKE2016.pdf http://eprints.utm.my/id/eprint/81604/ http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:120479 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Institution: | Universiti Teknologi Malaysia |
| Language: | English |
| Summary: | Harris Corner Detector (HCD) algorithm is widely used in many applications of image processing. Its performance with noisy images exceeds many other methods, in terms of accuracy and stability. Various methods are used to compare images and detect moving objects such as block matching but these methods are slow and have less accuracy. Moreover, the implementation of HCD has been proven to be computationally intensive, therefore, real-time streaming is difficult to achieve with sequential software implementation. This report presents the hardware implementation of HCD using Field-Programmable Gate Array (FPGA). The targeted board for the design is DE2-115 FPGA development board with an Altera Cyclone IV device. The architecture was tested using a SystemVerilog test-bench, enveloped by a MATLAB test-bench. The accuracy of the results obtained was tested visually and compared with the results of the same algorithm implemented in MATLAB. A maximum operational frequency of 170 MHz was achieved. The system uses 40% of the board’s logic elements. Resource utilization and timing performance are considerably balanced compared to recent works. |
|---|