ASIC implementation and optimization of 16 bit SDRAM memory controller

• Main Authors: Alias, Nurul Ezaila, Ishaak, Suhaila, Koo, Jian Hong, Loong, Michael Peng Tan, Hamzah, Afiq, Abdul Wahab, Yasmin
• Format: Conference or Workshop Item
• Published: 2020
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/92583/; http://dx.doi.org/10.1109/ICSE49846.2020.9166869
• Institution: Universiti Teknologi Malaysia

Last-level caches (LLC) often used to relay between the central processing unit (CPU) and the main memory. Most traditional processor used static-random-access-memory (SRAM) as the cache storage. Other technologies such as embedded dynamic-random-access-memory (eDRAM) and Synchronous Dynamic Random...