FPGA-based design of a math co-processor for the Amir CPU

Math coprocessors are vital components in modern computing to improve the overall performance of the system. The AMIR CPU is a homegrown softcore 32-bit CPU that can only handle integer numbers making it inadequate for high-performance real-time systems. The aim of this project is to design and deve...

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Main Author: Tan, Arthur Foo Yen
Format: Thesis
Language:English
Published: 2020
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Online Access:http://eprints.utm.my/id/eprint/93024/1/TanFooYenMSKE2020.pdf
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Institution: Universiti Teknologi Malaysia
Language: English
id my.utm.93024
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spelling my.utm.930242021-11-07T06:00:32Z http://eprints.utm.my/id/eprint/93024/ FPGA-based design of a math co-processor for the Amir CPU Tan, Arthur Foo Yen TK Electrical engineering. Electronics Nuclear engineering Math coprocessors are vital components in modern computing to improve the overall performance of the system. The AMIR CPU is a homegrown softcore 32-bit CPU that can only handle integer numbers making it inadequate for high-performance real-time systems. The aim of this project is to design and develop a math coprocessor for the AMIR CPU that can perform addition, subtraction, multiplication and division on IEEE-754 single precision floating-point numbers. The design of the math coprocessor is devised and improved based on past works on IEEE 754 floating-point operations and math coprocessor implementations. The architecture of the proposed math coprocessor consists of a control unit with instruction decode, floating-point computation unit and a register file. The architecture type is a serial controller with pipelined data path. The proposed math coprocessor retrieves instruction from the instruction register, decodes it, retrieves operands from the CPU register, performs computation then stores the results into the internal register, pending retrieval from the AMIR CPU. The proposed math coprocessor managed to achieve at least 99.999% accuracy for all four arithmetic operations with a maximum frequency of 63.8 MHz, while utilizing less than 30% of the available resource on board an Intel Cyclone IV EP4CE10E22C8 FPGA. The design is not without flaws as the proposed design has problems with instruction queueing due to the absence of an instruction buffer. Nevertheless, with further improvements and features, the proposed math coprocessor has the potential to enable the AMIR CPU to be used in a wide range of applications. 2020 Thesis NonPeerReviewed application/pdf en http://eprints.utm.my/id/eprint/93024/1/TanFooYenMSKE2020.pdf Tan, Arthur Foo Yen (2020) FPGA-based design of a math co-processor for the Amir CPU. Masters thesis, Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering. http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:135942
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
language English
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Tan, Arthur Foo Yen
FPGA-based design of a math co-processor for the Amir CPU
description Math coprocessors are vital components in modern computing to improve the overall performance of the system. The AMIR CPU is a homegrown softcore 32-bit CPU that can only handle integer numbers making it inadequate for high-performance real-time systems. The aim of this project is to design and develop a math coprocessor for the AMIR CPU that can perform addition, subtraction, multiplication and division on IEEE-754 single precision floating-point numbers. The design of the math coprocessor is devised and improved based on past works on IEEE 754 floating-point operations and math coprocessor implementations. The architecture of the proposed math coprocessor consists of a control unit with instruction decode, floating-point computation unit and a register file. The architecture type is a serial controller with pipelined data path. The proposed math coprocessor retrieves instruction from the instruction register, decodes it, retrieves operands from the CPU register, performs computation then stores the results into the internal register, pending retrieval from the AMIR CPU. The proposed math coprocessor managed to achieve at least 99.999% accuracy for all four arithmetic operations with a maximum frequency of 63.8 MHz, while utilizing less than 30% of the available resource on board an Intel Cyclone IV EP4CE10E22C8 FPGA. The design is not without flaws as the proposed design has problems with instruction queueing due to the absence of an instruction buffer. Nevertheless, with further improvements and features, the proposed math coprocessor has the potential to enable the AMIR CPU to be used in a wide range of applications.
format Thesis
author Tan, Arthur Foo Yen
author_facet Tan, Arthur Foo Yen
author_sort Tan, Arthur Foo Yen
title FPGA-based design of a math co-processor for the Amir CPU
title_short FPGA-based design of a math co-processor for the Amir CPU
title_full FPGA-based design of a math co-processor for the Amir CPU
title_fullStr FPGA-based design of a math co-processor for the Amir CPU
title_full_unstemmed FPGA-based design of a math co-processor for the Amir CPU
title_sort fpga-based design of a math co-processor for the amir cpu
publishDate 2020
url http://eprints.utm.my/id/eprint/93024/1/TanFooYenMSKE2020.pdf
http://eprints.utm.my/id/eprint/93024/
http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:135942
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