Utilizing IXP-2400 to Provision QoS for Real Time Services on IPv6 DiffServ Network
Providing Quality of Service (QoS) and Traffic Engineering (TE) capabilities in the internet is essential, especially in supporting the requirement of real- time traffic, as well as mission critical applications. Differentiated Services (DiffServ) is an emerging technology that provides QoS and traf...
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Main Authors: | , , |
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Format: | Article |
Language: | English |
Published: |
Faculty of Electrical Engineering
2008
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Subjects: | |
Online Access: | http://eprints.utm.my/id/eprint/9933/1/KashifSaleem2008_UtilizingIXP-2400toProvisionQoSforRealTime.pdf http://eprints.utm.my/id/eprint/9933/ http://www.fke.utm.my/elektrika/june08/paper8june08.pdf |
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Institution: | Universiti Teknologi Malaysia |
Language: | English |
Summary: | Providing Quality of Service (QoS) and Traffic Engineering (TE) capabilities in the internet is essential, especially in supporting the requirement of real- time traffic, as well as mission critical applications. Differentiated Services (DiffServ) is an emerging technology that provides QoS and traffic engineering features in Internet Protocol (IP) Network by programming the IXP2400 Intel Network Processor. Since the introduction of the network processors, there have been a number of network services developed based on the special-built, packet processing optimized programmable microprocessors. This paper is mainly concerns on how to deploy DiffServ in order to assess priority functionalities. A scheduling mechanism was developed on the IXP2400 network processor to provide QoS by maintaining priority of incoming packets based on criteria i.e. class of packets and traffic. The queuing mechanism improves the QoS of the traffic at the expense of some performance degradation. To reduce the performance degradation, a cache unit has been added into the operation of the QoS mechanism to cut down SRAM access during the lookup operation. A performance study was then
carried out to evaluate the performance of the QoS mechanism after adding the cache unit. The overall speed is enhanced and delay is minimized. At the same time, the mechanism can be implemented on the ENP-2611 Evaluation Board to verify the functionality of the application on hardware |
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