Study of time-dependent dielectric breakdown (TDDB) in 15MM junctionless FinFET
As MOSFETs already reached the limitation in terms of physical and electrical characteristic which is difficult to continue producing with MOSFET due to the level of difficulty and complexity. Although, FinFETs provide several advantages but there are some drawbacks of FinFETs such as higher fabrica...
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| Format: | Thesis |
| Language: | English |
| Published: |
2022
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/99382/1/ChngSzeLynMSKE2022.pdf http://eprints.utm.my/id/eprint/99382/ http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:150057 |
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| Institution: | Universiti Teknologi Malaysia |
| Language: | English |
| Summary: | As MOSFETs already reached the limitation in terms of physical and electrical characteristic which is difficult to continue producing with MOSFET due to the level of difficulty and complexity. Although, FinFETs provide several advantages but there are some drawbacks of FinFETs such as higher fabrication cost, difficult to control dynamic threshold voltage etc. Therefore, JL FinFETs has been proposed to overcome the shortcoming. The main difference of FinFETs and JL FinFETs is the presence of junctions and gradient of doping concentration between source and drain. Therefore, JL FinFETs offers higher scalability with lower cost, higher compatibility and additional design parameters like substrate doping concentration. In recent, reliability of device has become one of the major concerns when scaling to nano regime. There are many works on reliability studies have been done includes Negative Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI), Time Dependent Dielectric Breakdown (TDDB) that occurs in MOSFETs. However, the information regarding reliability issue for JL FinFETs is very limited. Therefore, the reliability issue of JL FinFETs become a primary concern and should be investigated. This project mainly discussed about TDDB including type of physical model, typical behavior, constant stress test. The aims of project are to design and simulate the 15nm JL FinFETs device structure and TDDB test applications. Synopsys Sentaurus TCAD will be used for the simulation purpose. The design parameter for n-channel JL FinFETs using 15nm as the gate length, and 10nm for width and height of the fin. Then, TDDB test with Constant Voltage Stress (CVS) method will be carried out by for approx. 10 years with 3 different stresses applied to analyze the threshold voltage shift of 15nm JL FinFETs before and after the stress applications for long-term reliability of the oxide. The stress voltage was determined as 0.9V, 1.35V and 1.8V. Besides, the test will be carried out with several oxide thickness such as 1nm, 2.5nm, 4nm, 6nm and 10nm with numerous types of oxide material like SiO2, HfO2 and Si3N4. According to the experimental result, JL FinFETs with the combination of Si3N4 provide the greatest time to failure compared to SiO2 and HfO2 with the highest range in threshold voltage shift which is 2.17% - 8.43%. |
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