Optimized Encoder Architecture for Structured Low Density Parity Check Codes of Short Length
This paper proposes an architecture for structured low density parity check encoder. The proposed architecture supports the limitation of input/output pins of field programmable gate array using division of information bits. The division of information bits generates latency of encoding. The propose...
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Main Authors: | , , |
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Format: | Conference or Workshop Item |
Published: |
2014
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Online Access: | http://eprints.utp.edu.my/11965/1/1569890711.pdf http://eprints.utp.edu.my/11965/ |
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Institution: | Universiti Teknologi Petronas |