FPGA-based hardware implementation of optical flow constraint equation of Horn and Schunck
In hardware implementation, there are different architectures that can represent the same algorithm into hardware. The different architectures are usually caused by using different number representations. In this work, two hardware architectures of optical flow constraint equation of Horn and Schunc...
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my.utp.eprints.119852017-01-19T08:22:04Z FPGA-based hardware implementation of optical flow constraint equation of Horn and Schunck Rustam, Ruzali Hamid, Nor Hisham Hussin, Fawnizu Azmadi In hardware implementation, there are different architectures that can represent the same algorithm into hardware. The different architectures are usually caused by using different number representations. In this work, two hardware architectures of optical flow constraint equation of Horn and Schunck (OFCE-HS) are presented and compared. The first architecture (OFCE-HS MZ) is previous work using full integer number to represent the architecture. The second architecture (OFCE-HS RH) is our work using combination between integer and fraction number to represent the architecture. Hardware designs of the architectures are performed using Xilinx System Generator through HW-SW co-simulation scheme. As a result, our proposed work has better performance compared to the previous work. It has the ability to reduce noise as well as hardware resources. 2012 Conference or Workshop Item PeerReviewed application/pdf http://eprints.utp.edu.my/11985/1/06306121.pdf Rustam, Ruzali and Hamid, Nor Hisham and Hussin, Fawnizu Azmadi (2012) FPGA-based hardware implementation of optical flow constraint equation of Horn and Schunck. In: 4th International Conference on Intelligent and Advanced Systems (ICIAS 2012), 12-14 June 2012, Kuala Lumpur. http://eprints.utp.edu.my/11985/ |
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In hardware implementation, there are different architectures that can represent the same algorithm into hardware. The different architectures are usually caused by using different number representations. In this work, two hardware architectures of optical flow constraint equation of Horn and Schunck (OFCE-HS) are presented and compared. The first architecture (OFCE-HS MZ) is previous work using full integer number to represent the architecture. The second architecture (OFCE-HS RH) is our work using combination between integer and fraction number to represent the architecture. Hardware designs of the architectures are performed using Xilinx System Generator through HW-SW co-simulation scheme. As a result, our proposed work has better performance compared to the previous work. It has the ability to reduce noise as well as hardware resources. |
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Conference or Workshop Item |
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Rustam, Ruzali Hamid, Nor Hisham Hussin, Fawnizu Azmadi |
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Rustam, Ruzali Hamid, Nor Hisham Hussin, Fawnizu Azmadi FPGA-based hardware implementation of optical flow constraint equation of Horn and Schunck |
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Rustam, Ruzali Hamid, Nor Hisham Hussin, Fawnizu Azmadi |
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Rustam, Ruzali |
title |
FPGA-based hardware implementation of optical flow constraint equation of Horn and Schunck |
title_short |
FPGA-based hardware implementation of optical flow constraint equation of Horn and Schunck |
title_full |
FPGA-based hardware implementation of optical flow constraint equation of Horn and Schunck |
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FPGA-based hardware implementation of optical flow constraint equation of Horn and Schunck |
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FPGA-based hardware implementation of optical flow constraint equation of Horn and Schunck |
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fpga-based hardware implementation of optical flow constraint equation of horn and schunck |
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2012 |
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http://eprints.utp.edu.my/11985/1/06306121.pdf http://eprints.utp.edu.my/11985/ |
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