Low-power RRAM Device based 1T1R Array Design with CNTFET as Access Device
A SPICE model of metal oxide based resistive random access memory (RRAM) devices is demonstrated in this paper having bipolar switching characteristics and utilizing carbon nanotube field effect transistor (CNTFET) in a 1T1R configuration. The growth and the dissolution of the conductive filament in...
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my.utp.eprints.248992021-08-27T06:38:43Z Low-power RRAM Device based 1T1R Array Design with CNTFET as Access Device Zahoor, F. Zulkifli, T.Z.A. Khanday, F.A. Fida, A.A. A SPICE model of metal oxide based resistive random access memory (RRAM) devices is demonstrated in this paper having bipolar switching characteristics and utilizing carbon nanotube field effect transistor (CNTFET) in a 1T1R configuration. The growth and the dissolution of the conductive filament in the oxide layer is the basis of the switching mechanism in this model. The model has been implemented in HSPICE simulation software for circuit level analysis. Initially, the simulation of memory cell with CNTFETs is carried out and later on 3�3 memory matrix is analyzed. The proposed design shows a reduction in power consumption as compared to RRAM cell utilizing metal oxide semiconductor field effect transistor (MOSFET) in a 1T1R configuration. © 2019 IEEE. Institute of Electrical and Electronics Engineers Inc. 2019 Conference or Workshop Item NonPeerReviewed https://www.scopus.com/inward/record.uri?eid=2-s2.0-85075635287&doi=10.1109%2fSCORED.2019.8896306&partnerID=40&md5=fab05c2372a008c06325875139d60b6c Zahoor, F. and Zulkifli, T.Z.A. and Khanday, F.A. and Fida, A.A. (2019) Low-power RRAM Device based 1T1R Array Design with CNTFET as Access Device. In: UNSPECIFIED. http://eprints.utp.edu.my/24899/ |
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A SPICE model of metal oxide based resistive random access memory (RRAM) devices is demonstrated in this paper having bipolar switching characteristics and utilizing carbon nanotube field effect transistor (CNTFET) in a 1T1R configuration. The growth and the dissolution of the conductive filament in the oxide layer is the basis of the switching mechanism in this model. The model has been implemented in HSPICE simulation software for circuit level analysis. Initially, the simulation of memory cell with CNTFETs is carried out and later on 3�3 memory matrix is analyzed. The proposed design shows a reduction in power consumption as compared to RRAM cell utilizing metal oxide semiconductor field effect transistor (MOSFET) in a 1T1R configuration. © 2019 IEEE. |
format |
Conference or Workshop Item |
author |
Zahoor, F. Zulkifli, T.Z.A. Khanday, F.A. Fida, A.A. |
spellingShingle |
Zahoor, F. Zulkifli, T.Z.A. Khanday, F.A. Fida, A.A. Low-power RRAM Device based 1T1R Array Design with CNTFET as Access Device |
author_facet |
Zahoor, F. Zulkifli, T.Z.A. Khanday, F.A. Fida, A.A. |
author_sort |
Zahoor, F. |
title |
Low-power RRAM Device based 1T1R Array Design with CNTFET as Access Device |
title_short |
Low-power RRAM Device based 1T1R Array Design with CNTFET as Access Device |
title_full |
Low-power RRAM Device based 1T1R Array Design with CNTFET as Access Device |
title_fullStr |
Low-power RRAM Device based 1T1R Array Design with CNTFET as Access Device |
title_full_unstemmed |
Low-power RRAM Device based 1T1R Array Design with CNTFET as Access Device |
title_sort |
low-power rram device based 1t1r array design with cntfet as access device |
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Institute of Electrical and Electronics Engineers Inc. |
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2019 |
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https://www.scopus.com/inward/record.uri?eid=2-s2.0-85075635287&doi=10.1109%2fSCORED.2019.8896306&partnerID=40&md5=fab05c2372a008c06325875139d60b6c http://eprints.utp.edu.my/24899/ |
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