Parallel form of the pipelined intermediate architecture for two-dimensional discrete wavelet transform
A lifting-based VLSI architecture for two-dimensional discrete wavelet transform (2-D DWT) for 5/3 and 9/7 algorithms, called, pipelined intermediate architecture was proposed by Ibrahim et al., which aim at reducing power consumption of the overlapped external memory access without using the expens...
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| Main Authors: | , |
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| Format: | Citation Index Journal |
| Published: |
2009
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| Subjects: | |
| Online Access: | http://eprints.utp.edu.my/417/1/paper.pdf http://www.scopus.com/inward/record.url?eid=2-s2.0-67649405062&partnerID=40&md5=9954a40f8f88f1033facc22319738b8d http://eprints.utp.edu.my/417/ |
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| Institution: | Universiti Teknologi Petronas |
| Summary: | A lifting-based VLSI architecture for two-dimensional discrete wavelet transform (2-D DWT) for 5/3 and 9/7 algorithms, called, pipelined intermediate architecture was proposed by Ibrahim et al., which aim at reducing power consumption of the overlapped external memory access without using the expensive line-buffer. In this paper, we explore parallelism in order to best meet real-time applications of 2-D DWT with demanding requirements in terms of speed, throughput, and power consumption. Therefore, 2-parallel and 3-parallel form of the single pipelined intermediate architecture are proposed. The 2-parallel and 3-parallel pipelined intermediate architectures achieve speedup factors of 2 and 3, respectively, as compared with single pipelined intermediate architecture proposed by Ibrahim et al.
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