Pipelined architecture for low density parity check encoder

• Main Authors: Anggraeni, Silvia, Hussin, Fawnizu Azmadi, Jeoti , Varun
• Format: Conference or Workshop Item
• Published: 2012
• Subjects: QA75 Electronic computers. Computer science; TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utp.edu.my/8826/1/06306129.pdf; http://dx.doi.org/10.1109/ICIAS.2012.6306129; http://eprints.utp.edu.my/8826/
• Institution: Universiti Teknologi Petronas

This paper proposes a pipelined architecture for low density parity check encoder by pipelining information bits and sub-matrices of parity check matrix (H) using two bit-wise operations. The two bit-wise operations are multiplication and exclusive-OR. The investigation is done by exploring two meth...