Design & simulation of an improved soft-switched synchronous buck converter
This paper proposes an improved soft switched synchronous buck converter in a fixed load condition. The switching energy can be fully recovered during current commutation phase in the gate driver while the diode conduction losses in the low and high side switches can be substantially reduced by empl...
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| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Published: |
2009
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| Subjects: | |
| Online Access: | http://eprints.utp.edu.my/94/1/paper.pdf http://www.scopus.com/inward/record.url?eid=2-s2.0-70349743707&partnerID=40&md5=fd7e127f60e3a47f7f06f935dd86f98b http://eprints.utp.edu.my/94/ |
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| Institution: | Universiti Teknologi Petronas |
| Summary: | This paper proposes an improved soft switched synchronous buck converter in a fixed load condition. The switching energy can be fully recovered during current commutation phase in the gate driver while the diode conduction losses in the low and high side switches can be substantially reduced by employing additional L and C resonant in the circuit. Using PSpice simulation, the optimization technique has been studied. From the predetermined pulse width of the generated signals, the optimized resonant inductor current is observed to generate less oscillation and hence lower the switching loss. In addition, an optimized dead time interval is inserted between high side and low side of the transistors in the synchronous buck converter to minimize their body diode conduction losses. The detailed operations of both circuits are analyzed. © 2009 IEEE.
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