System Verilog for Verification
Based on the bestselling first edition this extensively revised second edition includes the relevant changes that apply to the 2008 version of the SystemVerilog Language Reference Manual (LRM). Significant changes include: The revision of nearly every explanation and code sample The inclusion of...
Saved in:
| 主要作者: | |
|---|---|
| 格式: | 圖書 |
| 語言: | English |
| 出版: |
Springer
2017
|
| 主題: | |
| 在線閱讀: | http://repository.vnu.edu.vn/handle/VNU_123/26210 |
| 標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|
| 總結: | Based on the bestselling first edition this extensively revised second edition includes the relevant changes that apply to the 2008 version of the SystemVerilog Language Reference Manual (LRM). Significant changes include:
The revision of nearly every explanation and code sample
The inclusion of new chapters: "A Complete SystemVerilog Testbench" with a complete constrained random testbench for an ATM switch and "Interfacing with C" on the DPI (Directed Programming Interface)
The addition of 70 new examples including larger ones such as a directed testbench at the end of chapter four
An expanded index with 50% more entries and cross references. |
|---|