Generating Hardware Assertion Checkers

Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the life...

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Main Authors: Boulé, Marc, Zilic, Zeljko
Format: Book
Language:English
Published: Springer 2017
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Online Access:http://repository.vnu.edu.vn/handle/VNU_123/30894
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Institution: Vietnam National University, Hanoi
Language: English
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spelling oai:112.137.131.14:VNU_123-308942020-05-13T01:41:21Z Generating Hardware Assertion Checkers Boulé, Marc Zilic, Zeljko Engineering Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement (...) 2017-04-19T02:29:02Z 2017-04-19T02:29:02Z 2008 Book 978-1-4020-8585-7 http://repository.vnu.edu.vn/handle/VNU_123/30894 en 289 p. application/pdf Springer
institution Vietnam National University, Hanoi
building VNU Library & Information Center
country Vietnam
collection VNU Digital Repository
language English
topic Engineering
spellingShingle Engineering
Boulé, Marc
Zilic, Zeljko
Generating Hardware Assertion Checkers
description Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement (...)
format Book
author Boulé, Marc
Zilic, Zeljko
author_facet Boulé, Marc
Zilic, Zeljko
author_sort Boulé, Marc
title Generating Hardware Assertion Checkers
title_short Generating Hardware Assertion Checkers
title_full Generating Hardware Assertion Checkers
title_fullStr Generating Hardware Assertion Checkers
title_full_unstemmed Generating Hardware Assertion Checkers
title_sort generating hardware assertion checkers
publisher Springer
publishDate 2017
url http://repository.vnu.edu.vn/handle/VNU_123/30894
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