Design and implementation of an interleaved switched capacitor DC-to-DC buck converter on a 0.18u CMOS process

• Main Authors: Lacida, Earl Kenneth J., Marica, Grace Ann L., Perocho, Joshua James M., Tan-Afuan, Karl Ivan C., Verzosa, Katrina R.
• Format: text
• Language: English
• Published: Animo Repository 2013
• Subjects: Smart power grid; Electric power distribution; Electrical and Electronics; Engineering
• Online Access: https://animorepository.dlsu.edu.ph/etd_bachelors/11358
• Institution: De La Salle University

Since the smart grid is a complex system of metering nodes for power lines that is comprised of thousands of integrated smart nodes, the need for a small chip arises so as not be conspicuous and become a physical load to the power line. To do this, sensors and other circuits need to be incorporated into integrated circuits. A critical part of the chip would be the power supply circuit that needs to regulate the output levels to a constant voltage as well as supply the required current. The researchers proposed an Interleaved Switched-Capacitor DC-DC Buck Converter to serve as the integrated circuit’s power supply. The Switched-Capacitor DC-DC Buck Converter was designed to have the following specifications: (1) Provide a constant output voltage of 1 volt (2) provide a maximum current of 1 milliampere (3) regulate an input voltage ranging from 1.4 to 1.8 volts (4) has an efficient of at least 70%. The clock circuit was assumed to be ideal. A nominal clock frequency of 3.6MHz was used. The load and line regulation as well as the output voltage ripple were tested. The response of the circuit to half or double of the nominal clock frequency was also observed. The output voltage settling time was measured. The circuit was also tested in all five process corners. A 4:3 capacitor bank configuration was used as the main switched-capacitor converter. Thirty-two capacitor banks were connected in parallel and are interleaved used ideal clocks. The feedback control system comprises of an operational amplifier used as a comparator, a bandgap reference, and an SR flip-flop. The control circuit compares the output voltage of the switched-capacitor bank to the reference voltage of 1 volt and uses the SR flip-flop to generate a digital clock enable signal. This signal enables or disables the clock signal to regulate the output voltage. The designed Switched-Capacitor DC-DC Buck Converter exhibit a maximum efficiency of 72.266% at an input voltage of 1.4 volts in the SS process corner. The worst percent load regulation was 0.642%. The worst percent line regulation of the circuit is 11%. The biggest ripple voltage observed was 10.6% millivolts. Using half or double the nominal clock frequency does not have a huge effect on the regulator’s performance. Using a low clock frequency of 10kHz, however, does not have produce satisfactory results. In conclusion, the researchers successfully designed, layout, and simulated an Interleaved Switch-Capacitor DC-DC Buck Converter. All of the target specifications were net. The load and line regulation, the ripple voltage, and the settling time were also acceptable.