FPGA-Based digital image processing development platform to demonstrate JPEG compression using a CMOS image sensor and SD card storage

• Main Authors: Cham, Patrick T., Co, Mark Jordan D., Dagal, Rene Victor C., Jr., Lim, Alwyn John Y.
• Format: text
• Language: English
• Published: Animo Repository 2011
• Online Access: https://animorepository.dlsu.edu.ph/etd_bachelors/14443
• Institution: De La Salle University

This paper presents an FPGA based digital image processing platform that demonstrates a JPEG compression. The raw image comes from a CMOS camera module that is attached to the Altera DE2 development board. The compressed image is saved in an SD card after being processed by the hardware implemented image processing algorithms. The system is composed of two main parts namely the control subsystem and the hardware implemented digital image subsystem. The control system takes care of the data flow, and peripheral interfaces and controllers. The DIP subsystem is implemented in hardware in the FPGA chip which consists of the JPEG compression algorithms. This study makes use of a System-on-a-programmable-chip (SOPC) system to implement the control system. A programmable Nios II soft processor was also used to serve as the master peripheral for all of the modules in the whole system."