FPGA-based CISC and RISC microprocessor interfacing instructional training module

The advancement in microprocessor technology is rapidly increasing everyday. Since we are now in the Pentium age, other microprocessors have become obsolete. Microprocessors today are becoming more powerful, capable of performing faster and bigger tasks than ever before. As a result, microprocessor...

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Main Authors: Balboa, Marc Levin Y., Juan, Ivan Stanlley P., Pagalilauan, Arbee Jacob L., Sy, Peter John R.
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Language:English
Published: Animo Repository 2009
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Online Access:https://animorepository.dlsu.edu.ph/etd_bachelors/14458
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Institution: De La Salle University
Language: English
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spelling oai:animorepository.dlsu.edu.ph:etd_bachelors-151002021-11-04T08:11:11Z FPGA-based CISC and RISC microprocessor interfacing instructional training module Balboa, Marc Levin Y. Juan, Ivan Stanlley P. Pagalilauan, Arbee Jacob L. Sy, Peter John R. The advancement in microprocessor technology is rapidly increasing everyday. Since we are now in the Pentium age, other microprocessors have become obsolete. Microprocessors today are becoming more powerful, capable of performing faster and bigger tasks than ever before. As a result, microprocessor interfacing becomes harder and more complex. Students taking up courses related to microprocessors, such as computer organization, computer architecture, digital systems design and microprocessor systems, must learn and appreciate the basics of interfacing and architecture of the microprocessors before tackling the recent microprocessors being developed today. The problem is that it is very hard to find 8086-based trainer. RISC based system are becoming the mainstream in providing trainers for RISC processor but they are rather expensive or if not unavailable. This study attempts to provide a flexible training module using FPGA. CISC & RISC architecture can be configured on the FPGA and series of experiments. The training module will consist of five interfacing experiments: (1) the experiment trainer familiarization (memory and parallel port interfacing), (2) keyboard interfacing, (3) VGA monitor interfacing, (4) serial port interfacing and (5) debug monitor program which is an integration of all the interfacing experiments. Students will be provided VHDL microprocessor (one CISC and one RISC) codes to test the interfacing experiments given. Students will also be provided with a lab manual to aid them with the interfacing experiments that they will be doing. Experiments will be done on the Spartan 3E Starter Kit board. 2009-01-01T08:00:00Z text https://animorepository.dlsu.edu.ph/etd_bachelors/14458 Bachelor's Theses English Animo Repository Field programmable gate arrays Microprocessors Reduced instruction set computers Computer architecture Microprocessors--Design Pentium (Microprocessor)"
institution De La Salle University
building De La Salle University Library
continent Asia
country Philippines
Philippines
content_provider De La Salle University Library
collection DLSU Institutional Repository
language English
topic Field programmable gate arrays
Microprocessors
Reduced instruction set computers
Computer architecture
Microprocessors--Design
Pentium (Microprocessor)"
spellingShingle Field programmable gate arrays
Microprocessors
Reduced instruction set computers
Computer architecture
Microprocessors--Design
Pentium (Microprocessor)"
Balboa, Marc Levin Y.
Juan, Ivan Stanlley P.
Pagalilauan, Arbee Jacob L.
Sy, Peter John R.
FPGA-based CISC and RISC microprocessor interfacing instructional training module
description The advancement in microprocessor technology is rapidly increasing everyday. Since we are now in the Pentium age, other microprocessors have become obsolete. Microprocessors today are becoming more powerful, capable of performing faster and bigger tasks than ever before. As a result, microprocessor interfacing becomes harder and more complex. Students taking up courses related to microprocessors, such as computer organization, computer architecture, digital systems design and microprocessor systems, must learn and appreciate the basics of interfacing and architecture of the microprocessors before tackling the recent microprocessors being developed today. The problem is that it is very hard to find 8086-based trainer. RISC based system are becoming the mainstream in providing trainers for RISC processor but they are rather expensive or if not unavailable. This study attempts to provide a flexible training module using FPGA. CISC & RISC architecture can be configured on the FPGA and series of experiments. The training module will consist of five interfacing experiments: (1) the experiment trainer familiarization (memory and parallel port interfacing), (2) keyboard interfacing, (3) VGA monitor interfacing, (4) serial port interfacing and (5) debug monitor program which is an integration of all the interfacing experiments. Students will be provided VHDL microprocessor (one CISC and one RISC) codes to test the interfacing experiments given. Students will also be provided with a lab manual to aid them with the interfacing experiments that they will be doing. Experiments will be done on the Spartan 3E Starter Kit board.
format text
author Balboa, Marc Levin Y.
Juan, Ivan Stanlley P.
Pagalilauan, Arbee Jacob L.
Sy, Peter John R.
author_facet Balboa, Marc Levin Y.
Juan, Ivan Stanlley P.
Pagalilauan, Arbee Jacob L.
Sy, Peter John R.
author_sort Balboa, Marc Levin Y.
title FPGA-based CISC and RISC microprocessor interfacing instructional training module
title_short FPGA-based CISC and RISC microprocessor interfacing instructional training module
title_full FPGA-based CISC and RISC microprocessor interfacing instructional training module
title_fullStr FPGA-based CISC and RISC microprocessor interfacing instructional training module
title_full_unstemmed FPGA-based CISC and RISC microprocessor interfacing instructional training module
title_sort fpga-based cisc and risc microprocessor interfacing instructional training module
publisher Animo Repository
publishDate 2009
url https://animorepository.dlsu.edu.ph/etd_bachelors/14458
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