A Semi-custom based 8-bit 8051 compatible microcontroller core

• Main Authors: Arce, Ryan James S.M., Bautista, John Cedric D., Medalla, Kevin Thomas T., Sule, Danisha Khrizten S., Uy, Rheggy C.
• Format: text
• Language: English
• Published: Animo Repository 2012
• Online Access: https://animorepository.dlsu.edu.ph/etd_bachelors/14827
• Institution: De La Salle University

It is an implementation of an existing 8051 microcontroller core that had been modified to have a pipelined Verilog core design. The semi-custom based microcontroller core was developed to take the Integrated Circuits studies of De La Salle University farther by exploring the possibility of designing using popular architectures that are used not just for education purposes but also for innovation. In this thesis, we develop a working core which consists of modified controller, Arithmetic Logic Unit (ALU) and decoder from the existing 8051 architecture and of our own Program Counter, Parallel in/Parallel Out Register, multiplexer and generated memory blocks from Xilinx IPCore generator. With the combination of the modified blocks, generated memory components and our own modules, we implemented and synthesized the design into a standard core library using Synopsys. We also presented the testing, simulation and static timing analysis to demonstrate that the microcontroller core design performance. In addition, Synopsys is the main tool used that provided the synthesis, extraction of netlis and the IC layout of the 8051 microcontroller core. However, we have observed that the extracted netlist from it contains a large number of pages thus cannot be used for reverse simulation. As a result, this project shows that the development of such designs is helpful in the study of Integrated Circuits as well as the familiarity of the program used in the industry such as the Synopsys tools.